Each
operating system has its own methods for storing page tables.
Most
of them allocate a page table for each process. A pointer to the page table is
stored with the other register values in the process control block (PCB)
Hardware Support
The
hardware implementation of the page table can be done in a number of different
ways.
In
the simplest case, the page table is implemented as a “set of dedicated
registers”.
These
registers should be built with very high-speed logic to make the paging address
translation efficient.
CPU
dispatcher reloads these registers or modify the page-table registers.
DEC
PDP-11is an example of such an architecture.
Limitation
The
user of registers for the page table is satisfaction if the page table is
reasonably small (for example 256 entries)
Most
computers allow the page table to be very large (for example 1 million entries)
for these machine, the use of fast register to implement the page table is not
feasible.
Way – 2
Rather,
the page table is kept in main memory and a oage-table register (PBTR) points
to the page table.
Changing
page tables requires changing only this one register, which reduces context
switch time.
The
problem with this approach is the time require to access a user memory
location.
If
we want to access location , I, we must first index into the page table by the
page number for I, using the value in the PBTR offset. This task requires a
memory access.
It
gives us a frame number, which is combined with the page offset to produce the actual
address. Then we can access the desire place in memory.
With
this scheme, 2 memory accesses at needed to access a byte (one for the
page-table entry, one for the require byte).
The
memory access is slowed by a factor of 2. This delay would be intolerable under
most circumstances.